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s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) product overview 1 - 1 1 product overview s3c8-series microcontrollers samsung's s3c8-series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals and various mask-programmable rom sizes. important cpu features include: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. s3c80e5/c80e7 microcontroller the s3c80e5/c80e7 single-chip cmos microcontroller is fabricated using a highly advanced cmos process, based on samsung?s newest cpu architecture . the s3c80e5/c80e7 is the microcontroller which has 16/24-kbyte mask-programmable rom . the S3P80E5/p80e7 is the microcontroller which has 16/24-kbyte one-time-programmable eprom. using a proven modular design approach, samsung engineers developed the s3c80e5/c80e7 by integrating the following peripheral modules with the powerful sam87 core : ? four programmable i/o ports, including three 8 -bit ports and one 2-bit port, fo r a total of 26 pins. ? internal lvd circuit and twelve bit- programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabilization and watchdog functions (system reset) . ? one 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. ? one 8-bit counter with auto-reload function and one-shot or repeat control. the s3c80e5/c80e7 is a versatile general-purpose microcontroller which is especially suitable for use as unified remote transmitter controller. it is currently available in a 32-pin sop and sdip package for s3c80e5 and s3c80e7 . and available in 40 dip package only for s3c80e7. otp the S3P80E5/p80e7 is an otp (one time programmable) version of the s3c80e5/c80e7 microcontroller. the S3P80E5/p80e7 microcontroller has an on-chip 16/24-kbyte one-time-programmable eprom instead of a masked rom. the S3P80E5/p80e7 is comparable to the s3c80e5/c80e7, both in function and in pin configuration.
product overview s3 c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 1 - 2 feature s cpu ? sam8 7 cpu core m emory ? 16-kbyte internal program memory (rom) : s3c80e5 ? 24 -kbyte internal program memory (rom) : s3c80e7 ? 256 -byte internal (ram): 8000?80ffh ? data memory: 317- byte internal register file instruction set ? 78 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 75 0 ns at 8 mhz f osc (minimum) interrupts ? six interrupt levels and 18 interrupt sources ? 15 vectors (14 sources have a dedicated vector address and four sources share a single vector) ? fast interrupt processing feature (for one selected interrupt level) i/o ports ? three 8-bit i/o ports (p0?p2) and one 2-bit port (p3) for a total of 26 bit-programmable pins ? twelve input pins for external interrupts timer s and timer/counters ? one p rogrammable 8-bit basic timer (bt) for oscillation stabilization control or watchdog timer (software reset) function ? one 8-bit timer/counter (timer 0) with three operating modes; interval, capture, and pwm ? one 16-bit timer/counter (timer 1) with two operating modes ; interval and capture carrier frequency generator ? one 8-bit counter with auto-reload function and one-shot or repeat control (counter a ) back-up mode ? when reset pin is low level or when v dd is lower than v lvd , the chip enters back-up mode to reduce current consumption. low voltage detect circuit ? low voltage detect for reset or back-up mode input. ? low level detect voltage : 2.2 v (typ) ?100 mv/+ 200 mv operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 2.0 v to 5.5 v at 4 mhz f osc ? 2.1 v to 5.5 v at 8 mhz f osc package type ? 32-pin sop ? 32-pin sdip ? 40-pin dip
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) product overview 1 - 3 block diagram i/o port and interrupt control sam87 cpu internal bus 8-bit basic timer port2 x in x out program memory ( 16/24-kbyte program memory and 256-byte program ram) 317-byte register file p2.0?p2.3 (int5?int8) p2.4?p2.7 port 0 p1.0?p1.7 port 1 8-bit timer/ counter 16-bit timer/ counter carrier generator (counter a) reset test port 3 p3.1/rem/t0ck p3.0/t0pwm/ t0cap/t1cap p0.0?p0.7 (int0?int4) main osc v dd lvd figure 1-1. block diagram
product overview s3 c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 1 - 4 pin assignments v ss x in x out test p2.0/int5 p2.1/int6 p2.2/int7 p2.3/int8 p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p0.4/int4 p0.5/int4 p0.6/int4 p0.7/int4 v dd p3.1/rem/t0ck p3.0/t0pwm/t0cap/t1cap p2.7 p2.6 p2.5 p2.4 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 s3c80e5 s3c80e7 32-sop/sdip (top view) reset/back-up mode figure 1-2. pin assignment (32-pin sop/sdip package ) v ss x in x out test nc nc p2.0/int5 p2.1/int6 p2.2/int7 p2.3/int8 p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 nc nc p0.4/int4 p0.5/int4 p0.6/int4 p0.7/int4 v dd p3.1/rem/t0ck p3.0/t0pwm/t0cap/t1cap nc nc p2.7 p2.6 p2.5 p2.4 p1.7 p1.6 p1.5 p1.4 nc nc p1.3 p1.2 p1.1 p1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 s3c80e5 s3c80e7 40-dip (top view) reset/back-up mode figure 1-3. pin assignment (40-pin dip package )
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) product overview 1 - 5 table 1-1. pin descriptions pin names pin type pin description circuit type pin n o. (32-pin) pin n o. (40-pin) shared functions p0.0 ? p0.7 i/o i/o port with bit-programmable pins. configurable to input or push-pull output mode. pull-up resistors are assignable by software. pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. 1 9?16 11?14, 17?20 int0?int4 p1.0 ?p1.7 i/o i/o port with bit-programmable pins. configurable to c-mos input mode or output mode. pin circuits are either push- pull or n-channel open-drain type. pull-up resistors are assignable by software. 2 17?24 21?24, 27?30 ? p2.0?p2 .3 p2.4?p2.7 i/o general-purpose i/o port with bit- programmable pins. configurable to c- mos input mode, push-pull output mode, or n-channel open-drain output mode. pull-up resistors are assignable by software. lower nibble pins, p2.3?p2.0, can be assigned as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. 3 4 5?8, 25?28 7?10, 31?34 int5?int8 ? p3.0 p3.1 i/o 2-bit i/o port with bit-programmable pins. configurable to c-mos input mode, push- pull output mode, or n-channel open-drain output mode. pull-up resistors are assignable by software. the two port 3 pins have high current drive capability. 5 29 30 37 38 t0pwm/ t0cap/ t1cap/ rem/t0ck x in , x out ? system clock input and output pins ? 2, 3 2, 3 ? reset / back-up mode i system reset signal input pin and back-up mode input pin. the pin circuit is a c-mos input. 6 31 39 ? test i test signal input pin (for factory use only; must be connected to v ss ). ? 4 4 ? v dd ? power supply input pin ? 32 40 ? v ss ? ground pin ? 1 1 ?
product overview s3 c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 1 - 6 pin circuits pull-up resistor (typical 21 k w ) v dd i/o v ss data pull-up enable normal input output disable v dd interrupt input irq6,7 (int0-4) oscillator release (sed and r circuit) stop noise filter to prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic_ sed and r circuit - related to p0 and p1. this is a specific function for key input/output of universal remote controller. when these ports (p0, p1) are used as a normal input pin, unexpected stop mode recovery can occur by input level switching. hence, the user should be aware of input level switching, if p0 and p1 are to be used as normal input ports. note: figure 1- 4 . pin circuit type 1 ( port 0)
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) product overview 1 - 7 pull-up resistor (typical 21 k w ) v dd i/o v ss data pull-up enable output disable v dd normal input oscillator release (sed and r circuit) stop noise filter to prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic - sed and r circuit - related to p0 and p1. this is a specific function for key input/output of universal remote controller. when these ports (p0, p1) are used as a normal input pin, unexpected stop mode releasing can occur by input level switching. hence, the user should be aware of input level switching, if p0 and p1 are to be used as normal input ports. note: figure 1-5. pin circuit type 2 (port 1)
product overview s3 c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 1 - 8 pull-up resistor (typical 21 k w ) v dd i/o v ss data pull-up enable output disable v dd external interrupt irq5 (int5-8) noise filter open-drain normal input figure 1-6. pin circuit type 3 ( ports 2.0?2.3)
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) product overview 1 - 9 pull-up resistor (typical 21 k w ) v dd i/o v ss data pull-up enable output disable v dd open-drain normal input figure 1-7. pin circuit type 4 ( p2.4 - - p2.7)
product overview s3 c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 1 - 10 pull-up resistor (typical 21 k w ) v dd i/o v ss data pull-up enable output disable v dd open-drain normal input noise filter alternative input m u x port 3 data alternative output select figure 1-8. pin circuit type 5 ( p 3 ) back-up mode system reset reset/ back-up mode noise filter figure 1-9. pin circuit type 6 ( reset reset / back-up mode back-up mode )
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) electrical data 14 - 1 14 electrical data overview in this section, the s3c80e5/c80e7 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? characteristics of low voltage detect circuit ? data retention supply voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? stop mode release timing when initiated by a lvd ? i/o capacitance ? a.c. electrical characteristics ? input timing for external interrupts (port 0, p2.3?p2.0) ? input timing for reset ? oscillation characteristics ? oscillation stabilization time ? operating voltage range
electrical data s3c80e5/p80e5/c80e7 /p80e7 (p reliminary s pec ) 14 - 2 table 14 -1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in ? ? 0.3 to v dd + 0.3 v output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0, 1, and 2 + 100 total pin current for port 3 + 40 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 14 -2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.1 ? 5.5 v f osc = 4 mhz (instruction clock = 0.67 mhz) 2.0 ? 5.5 input high v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v voltage v ih2 reset 0.85 v dd v dd v ih3 x in v dd ? 0.3 v dd input low voltage v il1 all input pins except v il2 and v il3 0 ? 0.2 v dd v v il2 reset 0.4 v dd v il3 x in 0.3 output high voltage v oh1 v dd = 2.4 v; i oh = ? 6 ma port 3.1 only ; t a = 25 c v dd ? 0 .7 ? ? v v oh2 v dd = 2.4 v; i oh = ? 3 ma port 3.0 only ; t a = 25 c v dd ? 0.7
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) electrical data 14 - 3 table 14 -2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh3 v dd = 5 v; i oh = ? 3 ma port 2.7 only ; t a = 25 c v dd ? 0.25 ? ? v v dd = 2 v; i oh = ? 1 ma port 2.7 only ; t a = 25 c v oh4 v dd = 3.0 v; i oh = ? 1 ma all output pins except p3 and p2.7 port; t a = 25 c v dd ? 1 output low voltage v ol1 v dd = 2.4 v ; i ol = 15 ma port 3.1 only ; t a = 25 c ? 0.4 0.5 v v ol2 v dd = 2.4 v ; i ol = 5 ma port 3.0 only ; t a = 25 c 0.4 0.5 v ol3 i ol = 1 ma port 0, 1, and 2; t a = 25 c 0.4 1 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 1 a i lih2 v in = v dd , x in, and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out , and reset ? ? ? 1 a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 a output low leakage current i lol v out = 0 v all output pins ? ? ? 1 a pull-up resistor s r l1 v in = 0 v ; v dd = 2.4 v t a = 25 c ; ports 0?3 44 55 82 k w v dd = 5.5 v 15 21 32
electrical data s3c80e5/p80e5/c80e7 /p80e7 (p reliminary s pec ) 14 - 4 table 14 -2. d.c. electrical characteristics (con cl u d ed) (t a = ? 40 c to + 85 c, v dd = 2 v to 5.5 v) parameter symbol conditions min typ max unit supply current (n ote) i dd1 operating mode v dd = 5 v 10 % 8 mhz crystal ? 6 11 ma 4 mhz crystal 4.5 9 i dd2 idle mode v dd = 5 v 10 % 8 m hz crystal 1.8 3.5 4 mhz crystal 1.6 3 i dd3 stop mode v dd = 6 .0 v 20 35 m a v dd = 5.5 v 18 25 v dd = 3.3 v 12 15 v dd = 0.7 v 1.0 1.5 note : supply current does not include the current drawn through internal pull-up resistors or external output current loads. table 14 - 3 . characteristics of low voltage detect circuit (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit hysteresys voltage of lvd(slew rate of lvd) d v lvdcon = 10001111b ? 10 100 mv low level detect voltage v lvd lvdcon = 10001111b 2.10 2.20 2.40 v note: the reset values of bit 1 and bit 0 are in a unknown status, so is recommended to input the value #8fh in lvdcon for typical v lvd (2.2 v ?100/+200 mv). table 14 - 4 . data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.0 ? 5.5 v data retention supply current i dddr v dddr = 1 .0 v stop mode ? ? 1 a
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) electrical data 14 - 5 v dd ext int execution of stop instruction v dd > v lvd data retention mode stop mode normal operating mode t wait 0.2 v dd 0.8 v dd idle mode (basic timer active) ~ ~ ~ ~ figure 14 -1. stop mode release timing when initiated by a n external interrupt v dd reset execution of stop instruction data retention mode stop mode normal operating mode t wait oscillation stabilization time reset occurs ~ ~ ~ ~ note: t wait is the same as 4096 x 16 x v dd > v lvd 1/f osc . figure 14-2 . stop mode release timing when initiated by a reset reset
electrical data s3c80e5/p80e5/c80e7 /p80e7 (p reliminary s pec ) 14 - 6 v dd execution of stop instruction v dddr back-up mode stop mode normal operating mode t wait oscillation stabilization ~ ~ ~ ~ ~ ~ data retention mode reset occur v lv d note: t wait is the same as 4096 x 16 x 1/f osc . figure 14-3 . stop mode release timing when initiated by a lvd table 14 - 5 . input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 14 - 6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit interrupt input, high, low width t int h , t int l p0. 0?p0.7, p2.3?p2.0 v dd = 5 v 200 300 ? ns reset input low width t rsl input v dd = 5 v 10 00 ? ?
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) electrical data 14 - 7 t int l t int h 0.8 v dd 0.2 v dd note : the unit t cpu means one cpu clock period. figure 14-4 . input timing for external interrupts (port 0, p2.3?p2.0) back-up mode (stop mode) reset v dd reset occrurrs oscillation stabilization time normal operating mode t wait normal operating mode note: t wait is the same as 4096 x 16 x 1/f osc . figure 14-5 . input timing for reset reset
electrical data s3c80e5/p80e5/c80e7 /p80e7 (p reliminary s pec ) 14 - 8 table 14-7 . oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit crystal c2 c1 x in x out cpu clock oscillation frequency 1 ? 8 mhz ceramic c2 c1 x in x out cpu clock oscillation frequency 1 ? 8 mhz external clock s3c80e5 s3c80e7 external clock open pin x in x out x in input frequency 1 ? 8 mhz table 14-8 . oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator test condition min typ max unit main c rystal f osc > 400 khz ? ? 20 ms main c eramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 16 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? ms note s : 1. f osc is the oscillator frequency. 2. the duration of the o scillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon.
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) electrical data 14 - 9 instruction cl ock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 250 khz 500 khz 670 khz 1.00 mhz 8.32 khz instruction clock 1 2 3 4 5 6 7 f osc (main oscillation frequency) 6 mhz 4 mhz 400 khz 8 mhz 1.33 mhz 2.1 5.5 figure 14-6. operating voltage range of S3P80E5/p80e7
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) mechanical data 15 - 1 15 mechanical data overview the s3c80e5/c80e7 micr ocontroller is currently available in 32 -pin sop and sdip package. the s3c80e7 is also available in 40 dip package. 0 - 8 0.25 +0.10 - 0.05 8.34 0.2 0.90 0.20 10.02 0.1 #1 #16 #32 #17 32-sop-450a 12.00 0.2 note : dimensions are in millimeters. 19.90 0.05 0.10 max 0.05 min 2.00 0.1 2.30max (0.43) 0.40 0.1 1.27 figure 15-1. 32 -pin s o p package mechanical data
mechanical data s3c 80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 15 - 2 note : dimensions are in millimeters. 9.10 0.20 #1 #16 #32 #17 0 ? 15 * 0.25 +0.1 ? 0.05 10.16 0.51min 3.80 0.2 3.30 0.3 5.08max (1.37) 29.40 0.2 29.80 max 1.778 0.45 0.10 1.00 0.10 32-sdip-400 figure 15-2. 32 -pin s di p package mechanical data
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) mechanical data 15 - 3 note : dimensions are in millimeters. 15.24 0.25 + 0.1 ? 0.05 0.3 min 4.10 0.2 3.30 0.3 5.08max 5 2 .42 0.2 52.10 0.2 1.27 0.1 (1.92) 40-dip-600b 13.80 0.2 #1 #20 #40 #21 2.54 figure 15-3. 40 -pin di p package mechanical data
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) S3P80E5/p80e7 otp 16 - 1 16 S3P80E5/p80e7 otp overview the S3P80E5/p80e7 single-chip cmos microcontroller is the o tp ( one time programmable) version of the s3c80e5/c80e7 microcontroller. it has an on-chip eprom inst ead of a masked rom. the S3P80E5/p80e7 is ful ly compatible with the s3c80e5/c80e7 , both in function and in pin configuration. because of its simple programming requirements, the S3P80E5/p80e7 is ideal as an evaluation chip for the s3c80e5/c80e7 . v ss x in a14 (2) /x out mode /test pgm /p2.0/int5 mem_ reg /p2.1/int6 a8 /p2.2/int7 a9 / p2.3/int8 a 0 /p0.0/int0 a 1 /p0.1/int1 a 2 /p0.2/int2 a 3 / p0.3/int3 a 4 / p0.4/int4 a 5 / p0.5/int4 a 6 / p0.6/int4 a 7 / p0.7/int4 v dd p3.1/rem/t0ck/ ce p3.0/t0pwm/t0cap/t1cap/ oe p2.7/ a13 p2.6/ a12 p2.5/ a11 p2.4/ a10 p1.7/ d7 p1.6/ d6 p1.5/ d5 p1.4/ d4 p1.3/ d3 p1.2/ d2 p1.1/ d1 p1.0/ d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 S3P80E5 s3p80e7 32-sop/sdip (top view) reset / v pp notes: 1. the bolds indicate an otp pin name. 2. the address line 14 (a14) be used only for s3p80e7. figure 16-1. S3P80E5/p80e7 pin assignments of 32sop/32sdip
S3P80E5/p80e7 otp s 3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 16 - 2 v ss x in a14 /x out mode /test nc nc pgm /p2.0/int5 mem_ reg /p2.1/int6 a8 /p2.2/int7 a9 /p2.3/int8 a0 /p0.0/int0 a1 /p0.1/int1 a2 /p0.2/int2 a3 /p0.3/int3 nc nc a4 /p0.4/int4 a5 /p0.5/int4 a6 /p0.6/int4 a7 /p0.7/int4 v dd p3.1/rem/t0ck/ ce p3.0/t0pwm/t0cap/t1cap/ oe nc nc p2.7/ a13 p2.6/ a12 p2.5/ a11 p2.4/ a10 p1.7/ d7 p1.6/ d6 p1.5/ d5 p1.4/ d4 nc nc p1.3/ d3 p1.2/ d2 p1.1/ d1 p1.0/ d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 S3P80E5 s3p80e7 40-dip (top view) reset / v pp notes: 1. the bolds indicate an otp pin name. 2. the address line 14 (a14) be used only for s3p80e7. figure 16-2. S3P80E5/p80e7 pin assignments of 40dip
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) S3P80E5/p80e7 otp 16 - 3 table 16- 1. 32 sop/sdip pin descriptions u sed to r ead/ w rite the eprom pin name pin no. i/o function a0?a14 3, 7? 6, 25?28 o address lines to read/write eprom d0?d7 17?24 i/o 8-bit data input/output lines to read/write eprom mode 4 ? select eprom mode. ce 30 i chip enable (connect to v ss , when read/write eprom) oe 29 i output enable pgm 5 i eprom program enable mem_ reg 6 i select memory space of eprom v dd 32 ? supply voltage ( normally 5 v) v pp 31 ? eprom program/verify voltage (normally 12. 5 v) v ss 1 ? ground x in 2 ? system clock input pin characteristics of eprom operati on when +12.5 v is su pplied to v pp and mode pin s of the S3P80E5/p80e7 , the eprom programming mode is e ntered. the operating mode (read, write) is selected according to the input signals to the pins listed in table 16- 2 as below. table 16-2 . operating mode selection criteria v dd mode v pp pgm pgm mem mem oe oe mode 5 v v pp 1 2.5 v 1 1 0 read 0 1 1 program 1 1 0 program verify note : "0" means low level; "1" means high level.
S3P80E5/p80e7 otp s 3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 16 - 4 mode oe d7 - - d0 a14 - - a0 t oed t acc t oew t oeh 12.5v figure 16-3 . otp read timing table 16-3. o tp read char acteristics (t a = 25 c 5 c, v dd = 5 v 5 %, v pp = 12.5 v 0.25v ) parameter symbol min typ max units address to output delay t acc ? ? 75 ns oe to address delay t o ed 0 ? ? oe pulse width t o ew 75 ? ? output hold from oe whichever occurs first t oeh 0 ? ?
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) S3P80E5/p80e7 otp 16 - 5 pgm d7 - - d0 a14 - - a0 t oew t oe t oeh t pw t v s t ds data in stable data out valid program verify program t dh mode oe figure 16-4 . program memory write timing table 16-4 . o tp progra m/program verify characteristics (t a = 25 c 5 c, v dd = 5 v 5 %, v pp = 12.5 v 0.25 v ) parameter symbol min typ max units v pp setup time t vs ? 2 ? s data setup time t ds ? 2 ? data hold time t dh ? 2 ? pgm pulse width t pw ? 300 500 data valid from oe t o e 75 ? ? ns oe pulse width t o ew 75 ? ? output enable to output float delay t o e h 0 ? 130
S3P80E5/p80e7 otp s 3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 16 - 6 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16-5 . otp programming algorithm
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) S3P80E5/p80e7 otp 16 - 7 table 16 - 5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 8 mhz (instruction clock = 1.33 mhz) 2.1 ? 5.5 v f osc = 4 mhz (instruction clock = 0.67 mhz) 2.0 ? 5.5 input high v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v voltage v ih2 reset 0.85 v dd v dd v ih3 x in v dd ? 0.3 v dd input low voltage v il1 all input pins except v il2 and v il3 0 ? 0.2 v dd v v il2 reset 0.4 v dd v il3 x in 0.3 output high voltage v oh1 v dd = 2.4 v; i oh = ? 6 ma port 3.1 only ; t a = 25 c v dd ? 0 .7 ? ? v v oh2 v dd = 2.4 v; i oh = ? 3 ma port 3.0 only ; t a = 25 c v dd ? 0.7 output high voltage v oh3 v dd = 5 v; i oh = ? 3 ma port 2.7 only ; t a = 25 c v dd ? 0.25 ? ? v v dd = 2 v; i oh = ? 1 ma port 2.7 only ; t a = 25 c v oh4 v dd = 3.0 v; i oh = ? 1 ma all output pins except p3 and p2.7 port; t a = 25 c v dd ? 1 output low voltage v ol1 v dd = 2.4 v ; i ol = 15 ma port 3.1 only ; t a = 25 c ? 0.4 0.5 v v ol2 v dd = 2.4 v ; i ol = 5 ma port 3.0 only ; t a = 25 c 0.4 0.5 v ol3 i ol = 1 ma port 0, 1, and 2; t a = 25 c 0.4 1 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 1 a i lih2 v in = v dd , x in , and x out 20
S3P80E5/p80e7 otp s 3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) 16 - 8 table 16 - 5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max unit input low leakage current i lil1 v in = 0 v all input pins except x in , x out , and reset ? ? ? 1 a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 a output low leakage current i lol v out = 0 v all output pins ? ? ? 1 a pull-up resistor s r l1 v in = 0 v ; v dd = 2.4 v t a = 25 c ; ports 0?3 44 55 82 k w v dd = 5.5 v 15 21 32 supply current ( n ote) i dd1 operating mode v dd = 5 v 10 % 8 mhz crystal ? 6 11 ma 4 mhz crystal 4.5 9 i dd2 idle mode v dd = 5 v 10 % 8 m hz crystal 1.8 3.5 4 mhz crystal 1.6 3 i dd3 stop mode; v dd = 6 .0 v 20 35 m a v dd = 5.5 v 18 25 v dd = 3.3 v 12 15 v dd = 0.7 v 1.0 1.5 note : supply current does not include the current drawn through internal pull-up resistors or external output current loads.
s3c80e5/p80e5/c80e7/p80e7 (p reliminary s pec ) S3P80E5/p80e7 otp 16 - 9 instruction cl ock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) supply voltage (v) 250 khz 500 khz 670 khz 1.00 mhz 8.32 khz instruction clock 1 2 3 4 5 6 7 f osc (main oscillation frequency) 6 mhz 4 mhz 400 khz 8 mhz 1.33 mhz 2.1 5.5 figure 16-6. operating voltage range

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